JEDEC Unwraps LPDDR6 Memory Standard for Improved Computing in Edge AI, Data Center and Automotive Sectors

The adoption of AI in modern electronic systems is demanding rapid advancements in memory performance, power efficiency and security. Memory performance, in particular, is essential to facilitating a new era of smartphone and edge computing. Edge devices demand high-performance processing and greater memory bandwidth while maintaining low cost, power efficiency and reliability

To that end, the JEDEC Solid State Technology Association has announced the publication of JESD209-6, the latest Low-Power Double Data Rate 6 (LPDDR6) standard. JESD209-6 is designed to significantly boost memory speed and efficiency for a variety of uses. This standard reflects a step forward in delivering high-performance, low-power DRAM solutions with greater reliability across a wider range of use cases.

It will be deployed across various sectors, including AI edge computing, client systems, servers and the automotive industry to bring additional benefits to these devices including mobile devices and AI. JEDEC's newest memory standard, the successor to LPDDR5 and LPDDR5X, aims for higher performance, power efficiency and security.

“JEDEC is proud to introduce LPDDR6, the culmination of years of dedicated effort by members of the JC-42.6 Subcommittee for Low-Power Memories,” said Mian Quddus, JEDEC’s Chairman of the Board of Directors. He added, “By delivering a balance of power efficiency, robust security options and high performance, LPDDR6 is an ideal choice for next-generation mobile devices, AI and related applications to thrive in a power-conscious, high-performance world.”

High Performance

The new generation low-power memory LPDDR6 offers significant performance improvements to enable AI applications and other high-performance workloads, LPDDR6 employs a dual sub-channel architecture that allows for flexible operation while maintaining a small access granularity of 32 bytes. Its dual sub-channel architecture brings two sub-channels per die, each with 12 data signal lines (DQs).

Compared to LPDDR5, which has 16 DQ (2x8) lines per channel, PDDR6 reduces it to 2x12 for improved latency and access speed optimization. Each sub-channel includes 4 command/address (CA) signals, optimized to improve data access speed. Flexible data access also includes on-the-fly burst length control to support 32B and 64B burst lengths.

LPDDR6‘s on-die termination (ODT) is a technology where the termination resistor for impedance matching in transmission lines is located inside a semiconductor chip. Dynamic write NT-ODT (non-target on-die termination) enables the memory to adjust ODT based on workload demands, improving signal integrity.

Power Efficiency

With dynamic efficiency mode, LPDDR6 will allow a single sub-channel operation for low-power states and this will bring a noticeable improvement over LPDDR5 when it comes to power efficiency. A static efficiency mode is designed to support high-capacity memory configurations and maximize bank resource utilization.

LPDDR6 operates with a lower voltage to reduce dynamic power consumption as well as employing a low power consumption capable VDD2 supply as compared to LPDDR5 (the standard mandates two supplies for VDD2). It uses dynamic voltage frequency scaling for low power (DVFSL), a method of reducing the average power consumption in embedded systems.

This is accomplished by reducing the switching losses of the system by selectively reducing the frequency and voltage of the system. DVFSL lowers the VDD2 supply during low-frequency operation to reduce power consumption. This voltage reduction directly impacts power consumption, as power is proportional to the square of the voltage.

Security and Reliability

For security and reliability, LPDDR6 brings in ECC (on-die error correction) code. It is capable of supporting command/address (CA) parity, a feature in DDR memory systems that provides error detection for command and address signals. It ensures data integrity by checking for bit errors during transmission of these signals, which are crucial for controlling memory operations. LPDDR further features error scrubbing, and memory built-in self-test (MBIST) for enhanced error detection and system reliability.

In addition, to support DRAM data integrity, the standard employs PRAC (per row activation counting), and it has the Rowhammer mitigation technique introduced in the DDR5 standard. Rowhammer attacks exploit weaknesses in DRAM technology, causing unintended bit flips in neighboring memory rows through repeated access to an aggressor row. It works by embedding an activation counter within each DRAM row, tracking how many times that row has been activated. Other features are included to enhance overall system reliability by allocating specific memory regions for critical tasks, thus ensuring data integrity and catching memory errors.

First Users

In developing standards for the microelectronics industry, JEDEC utilized thousands of volunteers representing over 360 member companies working together with more than 100 JEDEC committees and task groups. The newly released LPDDR6 standard will offer enhanced performance, efficiency, security and reliability for mobile systems and is expected to be adopted by leading memory makers.

The first company to roll out memory IP alongside the newly ratified JESD209-6 LPDDR6 standard is Cadence, which recently announced the tape out of its LPDDR6/5X memory IP system solution, the industry’s first to support data rates of up to 14.4 Gbps. which is approximately 50% faster than previous LPDDR5X solutions. And Qualcomm will reportedly be the first customer to incorporate Samsung’s LPDDR6 RAM chips in its products, with its upcoming Snapdragon 8 Elite mobile platform that powers high-end Android smartphones.