AI-Driven Chip Designs Improve PPA and Productivity

Every month sees the launch of new tools, rules and technological advancements. And in every new design, there are time-consuming tasks that are necessary for the quality of the chip. Finding the optimal power, performance and area (PPA) for chips while adhering to stringent design rules involves a substantial number of input parameters that can lead to different sub-optimal results.

Consequently, engineering teams need help to keep up with the ever-increasing demands of chip design. Without help, it is not realistically possible for engineers to explore all combinations to find the best results in a given timeframe.

Generative AI (GenAI) is a type of artificial intelligence (AI) that uses machine learning to create new text, images, videos, audio, code and simulations. Code generation, one of the most promising applications for generative AI technology, can take on repetitive tasks such as design space exploration, verification coverage and test pattern generation.

This holds great promise for design engineers who can benefit from the instantaneous code generated by AI models to design, verify and test semiconductor devices. AI has the potential to free up time for engineering teams, allowing these experts to focus on value-added tasks such as differentiating their products.

In chip design, generative AI can automate layout and floor planning, optimize PPA and ensure adherence to design rules. By leveraging advanced algorithms, it can accelerate design and explore the design space, identifying optimal solutions that traditional methods might overlook. Generative AI can also streamline the verification process, reducing errors and improving design quality. Generative AI can also enhance quality control, detecting defects and anomalies that traditional methods might overlook.

Multi-die architectures consisting of heterogeneous integration of multiple dies, or chiplets, in a single package are fast becoming an ideal architecture for AI applications as well. Multi-die systems are an answer to the slowing of Moore’s law, providing advantages beyond what monolithic system-on-chip (SoC) designs are capable of.

For these reasons all major electronic design automation (EDA) suppliers are investing heavily to create AI-enhanced design tools. EDA juggernauts Cadence and Synopsys for example have introduced AI in their design flows. We’ll look at what both are offering.

How AI Techniques Can Be Applied to EDA

The Cadence Cerebrus Intelligent Chip Explorer is an artificial intelligence AI-driven, automated approach to chip design flow optimization. Block engineers specify the design goals and generative AI features within Cerebrus will optimize the design to meet these power, performance and area (PPA) goals in a completely automated way.

By adopting Cadence Cerebrus, it is possible for engineers to concurrently optimize the flow for multiple blocks, which is especially important for the large, complex SoCs needed today.

AI-driven Cadence Cerebrus is being utilized by Broadcom to accelerate the delivery of their 3nm and 5nm designs and achieve aggressive time to tapeout schedules. For example, the floorplan exploration capability helps automatically determine the optimal chip design floorplan, saving PPA. The AI model reuse capability enables Broadcom to apply previous design learnings to their next-generation designs, reducing the time to optimized results. Finally, the interface provides interactive analytics, offering valuable insights into design data and easy debug.

First unveiled with Cadence Cerebrus in 2021, and in its full scope at CadenceLIVE 2023, this solution comprises five applications that span from chip to system to product. It integrates with Cadence's existing design tools and platforms, enabling designers to leverage the power of generative AI without disrupting their workflows.

Cadence Virtuoso Studio brings generative AI to analog design. Virtuoso Studio utilizes reinforcement learning techniques to optimize system-level architectures, explore design tradeoffs and enhance overall system performance. Virtuoso Studio empowers designers to unlock new levels of productivity and efficiency in analog design.

The Cadence Verisium AI-Driven Verification Platform combines generative AI with advanced debug techniques to attack debugging and verification processes. The Verisium platform leverages reinforcement learning to automate the generation of test scenarios, optimize test coverage and accelerate the verification process

Finally, the Cadence Optimality Intelligent System Explorer is an application that leverages generative AI to optimize physics analysis and the overall design workflow.

Synopsys.ai provides AI-driven solutions for chip design, with digital and analog, verification, test and manufacturing components. Launched in March 2023, Synopsys.ai is a full-stack, AI-driven EDA suite. The suite currently includes:

• Synopsys DSO.ai, which autonomously searches for optimization targets in a chip design’s very large solution spaces,
• Synopsys VSO.ai, which autonomously achieves faster verification coverage closure and regression analysis for faster functional testing closure, higher coverage and predictive bug detection and
• Synopsys TSO.ai, which automatically searches for optimal solutions in large test search spaces to minimize pattern count and turn-around time, reducing test costs dramatically and accelerating time to results.

NVIDIA, TSMC, IBM, MediaTek and Renesas all support Synopsys' AI-driven EDA design strategy with significant benefits already being seen. Renesas says it achieved a 10x improvement in reducing functional coverage holes and up to 30% increase in IP verification productivity. Renesas adds that it is using Synopsys.ai to shave weeks off product development times with enhanced silicon performance and cost reduction.

Summary

Chip design projects generate huge amounts of design data. Generative AI can help engineers sift through this mountain of data on the way to creating a final layout for manufacturing. Thus, what was once a problem is now increasingly seen as a great opportunity for applying AI techniques. Engineers can now use AI at every stage of chip design, from system architecture to design and manufacturing and access solutions in the cloud.

By overcoming the challenges of the traditional design process, generative AI can enable designers to create optimized, innovative, and customized solutions.