DAC 2016: Preparing for the Future of Electronics Design

The Design Automation Conference (DAC) is the Electronic Design Automation (EDA) industry’s annual flagship conference. DAC offers education, exhibits and networking opportunities for designers, researchers, tool developers, and vendors. Conferences such as DAC are important because successful engineers must treat their careers as dynamic things which need continuous upkeep and upgrading. One would be uncomfortable visiting a physician who has fallen behind in the practice of medicine. Similarly, an engineer’s skillset will become diminished without continuing education, especially since the pace of technological change these days can make your head spin—even given that engineers are positively predisposed to new technology.

The type of exhibitors at DAC 2016 was more varied than in previous years. The benefit of a more widely spread out show is it provides something for everyone, in this case offering solutions for the total system, not just its electronic parts. A few years ago the EDA industry realized that the role of hardware and software was changing. Software is increasingly being used to substitute for hardware to implement system tasks. As a consequence it became necessary to verify these systems and as a further result virtual prototyping and software/hardware verification has grown rapidly within EDA.

EDA companies, in turn, are deriving more income from providing embedded software than was true not very long ago. Similarly, their customers are hiring software engineers at a rate some have suggested is 3:1 (or more) compared to hardware engineers.

As for industry trends, Mentor Graphics CEO and Chairman Dr. Walden C. (Wally) Rhines noted that “we are in a more disruptive period than usual with regard to design challenges” but quickly added “that is how the EDA industry grows.” He said that while design tools for the PCB market, for example, might not be growing per se, concentration on signal integrity for PCBs is growing at a good pace and is driving that market segment. He added that emulation was growing rapidly as well “as we approach the 10nm, 7nm and even 5nm nodes.”

As is always the case at semiconductor industry events the status of Moore’s Law once again came to the forefront. Synopsys Chairman and co-CEO Dr. Aart de Geus tackled the question head on: “It’s like Habeas Corpus, show me the body. Moore’s Law has been declared dead for years and yet has found ways to circumvent death. Seven, eight and nine years ago I remember everyone decided that FInFets wouldn’t work” (and now of course FinFETs in logic and 3D-NAND in memory have become mainstream and the complexity of new process nodes has increased significantly). He concluded: “I believe we have at least ten more years left (with regard to) Moore’s Law.”

Here are some notable developments from the DAC show floor:

Faster PCB design and verification. New releases from Cadence are aimed at improving the interoperability between its Allegro and Sigrity tools to shorten PCB design and verification time. Cadence’s Allegro 17.2-2016 now features in-design inter-layer checking technology that reduces design-check-redesign iterations and a new dynamic concurrent-team-design capability aimed at accelerating product creation time (by up to 50 percent, according to the company). Embedded Sigrity technology ensures critical signals meet performance criteria and power integrity (PI) for PCB designers addressing power delivery and eliminating time-consuming iterations with PI experts. Cadence’s OrCAD 17.2-2016 release tackles PCB development time in the design of reliable circuits for smaller, more compact devices. It offers new capabilities for OrCAD Capture, PSpice Designer and PCB Designer that take on challenges with flex and rigid-flex design as well as mixed-signal simulation complexities in IoT, wearables and wireless mobile devices.

Single interface for SI and PI analysis. Keysight EESof Advanced Design System (ADS) 2016 software is said to improve design productivity and speed circuit and electromagnetic simulation performance. For example, while Signal Integrity (SI) and Power Integrity (PI) are often treated as separate design tasks that are closely interrelated, as part of its ADS 2016 Keysight offers a new single user interface for both PI and SI analyses: SIPro and PIPro. SIPro focuses on enabling SI EM analysis of high-speed links on large, complex high-speed PCBs, while PIPro is used for PI EM analysis of power distribution. SIPro enables you to characterize loss and coupling of signal nets, and ultimately extract an EM-accurate model and PIPro provides power integrity analysis of a power distribution network (PDN), including DC IR drop analysis, AC impedance analysis and power plane resonance analysis.

The work flow for SiPro and PiPro includes design import, analysis setup, simulation and automatic schematic generation for further simulation. Once in ADS, the design is opened in the SIPro / PIPro analysis environment where it is viewed, zoomed and rotated in 3D.

Mixed Signal Design flow for ARM Cortex-M0. Mentor Graphics announced a collaboration with ARM to provide access to Mentor’s Tanner AMS analog/mixed-signal design flow for ARM Cortex-M0 processor-based implementations, as part of the ARM DesignStart program. DesignStart offers SoC designers access to free Cortex-M0 processor IP for design, simulation, and prototyping, with the option of then purchasing a simplified fast-track license for commercialization.

The Tanner design flow supports digital, analog and MEMS design in one integrated, end-to-end flow. Designers capture the schematic, perform analog and mixed-signal simulation, and layout and verify the physical design. Designers will be able to evaluate an ARM Cortex-M0 IoT reference design at no cost by using a web-based Mentor Virtual Lab to interact with the complete set of Tanner design tools. After evaluation, customers can purchase the software from Tanner to begin creating their own IoT designs and combine this with the free Cortex-M0 design access available on the ARM DesignStart portal.

Power modeling to better predict SoC power and performance. Every SoC design team is grappling with the continued need to reduce power consumption. One way to accomplish this is through improved power modeling techniques that better predict SoC power and performance. Right now there’s no commonly accepted way to develop an accurate estimation of power consumption early in the design phase. Silicon Integration Initiative (Si2), an Austin-based integrated circuit research and development joint venture, has launched a project to help designers reduce power consumption. The project will develop new power modeling technology to estimate power consumption more easily and more accurately throughout the design process, especially during the earliest stages. The end result will be a new power modeling standard to reduce resources and costs needed to develop virtually every type of SoC. The specification will be contributed to the IEEE P2416 Standards Working Group for industrywide distribution.

Analog and Mixed-Signal Design Software. The Intento Design Methodology is based on its ID-Xplore tool. The tool reduces the latency of circuit sizing by automating the analog design process from hand analysis to simulation. Using ID-Xplore, designers can input the desired parameters of complex analog functions, and “explore” schematic options to achieve the right balance of performance, power consumption and robustness for a wide range of connected applications. Adding this new level of automation to the development cycle accelerates the design and technology migration of analog and mixed-signal IP. ID-Xplore can sit after an open-access analog IP database such as might be used with Cadence's Virtuoso and ahead of Cadence's Spectre analog simulator. Typical circuits include amplifiers and reconfigurable filters.

Pre-wafer simulation solution reduces process node development time. To meet the performance, power, area and cost targets of the 10-nm process node and beyond, semiconductor manufacturers need to evaluate a larger number of process options, device architectures and materials, and account for design criteria in selecting the best options. Toward that end Synopsys announced a pre-wafer simulation solution to help semiconductor manufacturers reduce process node development time. The new solution provides a process, transistor and circuit simulation flow that is claimed to enable technology development and design teams to evaluate various transistor and process options using a design technology co-optimization methodology that starts in the pre-wafer research phase. The generation of SPICE models, design rules and parasitics from TCAD and lithography simulations allow the creation of early process design kits to evaluate the performance, power, area and cost of a new process node. By narrowing down of process and device options the number of expensive and time-consuming wafer-based iterations can be reduced.