Passive and active components traditionally are mounted on the surface of a PC board (PCB). But while component size, ball pitch and line width have been decreasing over the years, in the future it will be much more difficult to increase packaging density. Consequently, as designs run out of space in which to place components there is once again renewed interest in embedding components inside of a substrate.
With that in mind the Packaging Committee of PSMA (Power Sources Manufacturers Association) commissioned and now has published a comprehensive study on using embedded substrate technology for building power sources. The report, titled "Current Developments in 3D Packaging with Focus on Embedded Substrate Technologies," was created in response to demand in the power industry for accelerated development of higher density, more efficient power sources.
PSMA's 340-page report was prepared under contract by LTEC Corporation with work subcontracted to Anagenesis and the Fraunhofer-Institute, and is based on the Packaging Committee's extensive research of over 750 articles and papers, analysis of 450 presentations/papers, and 30 industry expert interviews.
The study defines two classes of embedded components: discrete devices termed "inserted" components where the surface mount passive device (resistors, capacitors and inductors) are manufactured prior to assembly in the printed circuit board; and "formed" components that are manufactured as elements within the PCB. All three types of passives can be formed in an embedded substrate.
The PSMA report provides detailed analysis of substrates (organic and inorganic), components (actives and passives), thermal management, high temperature die, packaging technologies, interposers, as well as additive manufacturing and laser fabrication. Each passive component (resistors, capacitors, inductors) has an entire chapter which among other things details which suppliers are currently shipping products usable in power sources.
The report contains information on the core technologies required for embedding components in a PCB substrate and discusses companies currently engaged in the practice. For example, AT&S (Austria Technologie & Systemtechnik) has an Embedded Component Packaging (ECP) process that embeds discrete passives into the core of a PCB, reducing the package form factor by 30-50% for improved functionality and system performance. The AT&S process utilizes large (18 x 24-in.) panels and claims a greater than 99% yield. The AT&S process also is used by Texas Instruments and GaN Systems for embedding semiconductor devices.
TDK has developed its own process called Semiconductor Embedded in Substrate (SESUB), a technology where, as the name suggests, semiconductor chips thinned down to as low as 50 μm are embedded in a substrate. The whole thickness of the SESUB substrate, including the integrated semiconductor chips, is just 300 μm. All surfaces of the chip are in full contact with the laminate, which optimizes the heat transfer from the semiconductor into the substrate layers. The layers themselves contain the copper interconnection grids, which provide for efficient heat dissipation.
TDK's embedded process is said to be suitable for high density power supply modules or subsystems. Another benefit of SESUB is the ability to have complete metal shielding of the package, an attractive feature for EMI reduction.
General Electric's Power Overlay Technology (POL) is backed by a portfolio of over 300 patents. In POL a thin layer of polyimide sheet is laminated to a metal frame. The film is then coated with adhesive, the adhesive is UV cured and vias are laser machined or mechanically punched through the film. These vias provide openings for the power interconnect to the top layer. Circuit patterns are achieved by the application of photoresist and chemical etching processes. Layers can be added as dictated by interconnect requirements and low-profile passive components can be embedded into the overlay. Advantages include elimination of wire bonds with metal interconnections, higher performance – reduced interconnection parasitics allow for higher frequency operation—and improved thermal performance; two-sided heat removal becomes possible.
Schweizer AG's P2Pack process was developed as an early alternative to direct-bond-copper (DBC) for high current inverters, converters, and industrial motor drives. With P² Pack technology it is possible to build very thin modules which have less losses and improved heat dissipation characteristics; the P²Pack's construction is open to the bottom side of the PCB. A heat sink can easily be installed either using a Thermal Interface Material or using sintering technologies to further reduce thermal resistance from junction to ambient.
The PSMA report also describes Shinko's MCEP process as well as additional processes from Fujikara, Infineon, Semikron and Wurth Electronik.
For more information on 3D embedded packaging the co-chairs of the PSMA Packaging Committee, Ernie Parker of Crane Aerospace & Electronics and Brian Narveson of Narveson Consulting recently published summary articles with supporting illustrations based on the report in the online industry publications Electronic Products and EDN. The full PSMA report on 3D packaging is provided free of charge to PSMA Regular and Associate members. Affiliate members can purchase the report for the reduced price of $190. Others interested in the complete report may order a copy from PSMA for $2,990.