ISSCC 2015: 10nm, Power Management and a New Approach to Chip-to-chip Interconnect

IEEE's 2015 International Solid-State Circuits Conference (ISSCC) took place Feb. 22-26 in San Francisco. The theme of ISSCC 2015 was "novel system and circuit solutions which open new vistas for society, with opportunities for new lifestyles, all driven by Big Data technology." Papers and talks were presented on advances in circuits and technology with regard to next-generation fabrication nodes, low-power systems, wireless power and data transmission, and 3D IC structures.

Moore's Law: Still Viable

As is well known, Intel co-founder Gordon Moore predicted in 1965 that the transistor count of high-end processors would double every two years, and that has largely held true until now despite the mounting challenges of fabricating smaller transistors. Now with Moore's Law in its 50th year, Intel believes there is no reason for it to break down as transistor widths shrink to 10nm and below. In a panel session entitled "Moore's Law Challenges Below 10nm: Technology, Design and Economic Implications," Intel's Mark Bohr, senior fellow for logic technology development, noted that scaling continues to provide cheaper transistors, but cost reduction was still needed in order to justify new process technology. As a company, Intel believes Moore's Law will still be valid beyond the 10nm node, but says achieving this will require new materials and device structures, as well as close collaboration between process development and product design teams. Intel has stated that it expects the 10nm transition to occur smoothly in 2016, followed by a shrink to 7nm in 2018. Bohr noted last fall that Intel has developed a roadmap for pushing to 7nm and has indicated it may not need measures like Extreme Ultraviolet Lithography (EUV) to get there.

Power Management Advances

Of course there are other ways to implement improvements in addition to traditional technology scaling. For example, at ISSCC AMD emphasized advanced power management technologies in its upcoming A-Series Accelerated Processing Unit (APU) for notebooks and low-power desktops. Codenamed "Carrizo," the processors use a System-on-Chip (SoC) design and, according to AMD, will reduce the power consumed by the x86 cores alone by 40 percent, while also providing "substantial gains" in CPU, graphics, and multimedia performance. Carizzo will have 29 percent more transistors – 3.1 billion – than the prior generation ("Kaveri") without increasing die size, and while continuing to use the 28nm manufacturing process. It will launch by the middle of 2015.

How AMD is optimizing power is interesting. Using a technology called adaptive voltage and frequency scaling (AVFS) the unit analyzes voltage fluctuations on a nanosecond scale and compensates on the fly, so it does not supply too much current as compensation. Unique, patented high speed voltage sensors go beyond the usual measurements of thermal output and current draw in order to help the processor dynamically scale to workloads. The sensors enable each individual APU to adapt to its particular silicon characteristics, platform behavior, and operating environment. By adapting in real time to these parameters, AVFS can lead to up to 30 percent power savings, according to AMD.

FinFETS and Chip Interconnects

A few papers were presented at ISSCC describing the initial designs made in 16 and 14 nm FinFET processes by IBM, Samsung, and TSMC. Samsung, for example, started mass-producing 14nm FinFET chipsets in January and is using a 14nm FinFET technology based Exynos 7 processor inside its new Galaxy S6 top-end smartphone.

During ISSCC Samsung noted that it is already developing 10nm FinFET technology and Dr. Kinam Kim, president of Samsung Electronics Co Ltd., confirmed during a keynote talk that "there are no fundamental difficulties until 5nm." In terms of the resolution of lithography technology for semiconductor volume production, it is possible to realize a resolution of 3.25nm by combining EUV (extreme ultraviolet) and quadruple patterning, Kim said. Samsung noted at the conference that it had already successfully operated a FinFET with a gate length of 3.8nm in an R&D prototype device.

Also at the International Solid-State Circuits Conference Kandou Bus (Lausanne, Switzerland) received the Jan Van Vessem Award for Outstanding European Paper. The 2014 paper was entitled "A Pin- and Power-Efficient Low-Latency 8-to-12Gb/s/wire 8b8w-Coded SerDes Link for High-Loss Channels in 40nm Technology."

The paper describes Chord Signaling, a new approach to chip-to-chip interconnect where many of the implementation challenges are different from traditional approaches. Chord signaling transmits correlated signals across multiple wires, the same way that differential signaling sends correlated signals across two wires. Chord Signaling methods can be therefore looked at as a vast generalization of differential signaling. Through a comparator network, signals are received and translated into bits resulting, the company says, in 50% lower power consumption and higher pin-efficiency which translates to fewer pins for a given throughput. Better immunity to noise is said to be another benefit.

Applications of Chord Signaling are expected to range from in-package chip interconnect to multiple next generation memory interfaces to backplane and even long haul links. Chord Signaling is also easily adaptable to the unique requirements of virtually any chip-to-chip interface, according to Kandou.

Kandou has begun to develop products based on Chord Signaling with its first hard IP optimized for in-package chip interconnect. The solution, which utilizes Kandou's 5-bit over 6-wire "Glasswing" Chordal Code, is said to deliver 125Gbps and consume less than one pico-Joule per bit of energy. The IP will be fully tested, characterized and available for implementation in customer silicon later this year.